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preliminary rev. 0.6 6/01 copyright ? 2001 by silicon laboratories SI5310-ds06 this information applies to a product under development. its characteristics and specifications are subject to change without n otice. SI5310 p recision c lock m ultiplier /r egenerator ic features complete precision clock multiplier and clock regenerator device: applications description the SI5310 is a fully integrated low-power clock multiplier and clock regenerator ic. the clock multiplier generates an output clock that is an integer multiple of the input clock. the clock regenerator operates simultaneously, creating a ?clean? version of the input clock by using the clock synthesis phase-locked loop (pll) to remove unwanted jitter and square up the input clock?s rising and falling edges. the SI5310 uses silicon laboratories patented dspll ? architecture to achieve superior jitter performance while eliminating the analog loop filter found in traditional pll designs with a digital signal-processing algorithm. the SI5310 represents a new standard in low jitter, small size, low power, and ease-of-use for clock devices. it operates from a single 2.5 v supply over the industrial temperature range (?40c to 85c). functional block diagram ! performs clock multiplication to one of two frequency ranges: 150?167 mhz or 600?668 mhz ! jitter generation as low as 0.5 ps rms for 622 mhz output ! accepts input clock from 9.4?668 mhz ! regenerates a ?clean?, jitter- attenuated version of input clock ! dspll? technology provides superior jitter performance ! small footprint: 4 mm x 4 mm ! low power: 310 mw typical ! sonet/sdh systems ! terabit routers ! digital cross connects ! optical transceiver modules ! gigabit ethernet systems ! fibre channel dspll tm phase-locked loop buf buf clkin+ clkin? 2 multsel refclk+ refclk? 2 2 2 lol multout+ multout? clkout+ clkout? bias gen rext buf calibration regeneration pw rdn/cal ordering information: see page 20. pin assignments SI5310-bm gnd pa d 15 14 13 12 11 pw rd n clkout+ vd d clkout? vd d 1 2 3 4 5 vd d gnd refclk? rext refclk+ 20 19 18 17 16 nc m ultsel multout? multout+ gnd 6 7 8 9 10 lol gnd clkin+ clkin? vd d p reliminary d ata s heet
SI5310 2 preliminary rev. 0.6
SI5310 preliminary rev. 0.6 3 t able of c ontents section page detailed block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 dspll? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 clock multiplier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 1x multiplication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 clock regeneration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 reference clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 dspll lock detection (loss-of-lock) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 pll performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 device power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 pll self-calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 device grounding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 bias generation circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 differential input circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 differential output circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 pin descriptions: SI5310-bm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 ordering guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 bm package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 contact information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2
SI5310 4 preliminary rev. 0.6 detailed block diagram figure 1. detailed block diagram clkin? multout+ multout? clkout+ clkout? lol refclk+ refclk? pwrdn/cal multsel retime bias generation rext clkin+ refclk+ retime regen bias generation bias generation phase detector phase detector phase detector a/d dsp vco clk divider n lock detector c c calibration
SI5310 preliminary rev. 0.6 5 electrical specifications figure 2. differential voltage measurement (clkin, refclk, clkout, multout) figure 3. clkin to clkout, multout phase relationship figure 4. clock input and output rise/fall times table 1. recommended operating conditions parameter symbol test condition min 1 typ max 1 unit ambient temperature t a ?40 25 85 c SI5310 supply voltage 2 v dd 2.375 2.5 2.625 v notes: 1. all minimum and maximum specifications are guaranteed and apply across the recommended operating conditions. typical values apply at nominal supply voltages and an operating temperature of 25c unless otherwise stated. 2. the SI5310 specifications are guaranteed when using the recommended application circuit (including component tolerance) of figure 5 on page 11. v is v id ,v od differential i/os differential voltage swing differential peak-to-peak voltage signal + signal ? (signal +) ? (signal ?) v icm , v ocm v t t ci-m multout clkin clkout t m-co 1/f mult clkin, refclk, clkout, multout t f t r 80% 20%
SI5310 6 preliminary rev. 0.6 table 2. dc characteristics, v dd = 2.5 v, 622 mbps (multsel = 0) (v dd = 2.5 v 5%, t a = ?40c to 85c) parameter symbol test condition min typ max unit supply current multsel = 0 multsel = 1 i dd ? ? 117 124 127 134 ma power dissipation multsel = 0 multsel = 1 p d ? ? 293 310 333 352 mw common mode input voltage (clkin, refclk) v icm see figure 2 ? .80 " v dd ?v input voltage range* (clkin+, clkin?, refclk+, refclk?) v is see figure 2 ? ? 750 mv differential input voltage swing* (clkin, refclk) v id see figure 2 200 ? 1500 mv (pk-pk) input impedance (clkin, refclk) r in line-to-line 84 100 116 ? differential output voltage swing (clkout) v od 100 ? load line-to-line tbd 940 tbd mv (pk-pk) differential output voltage swing (multout) v od 100 ? load line-to-line tbd 900 tbd mv (pk-pk) output common mode voltage (clkout, multout) v ocm 100 ? load line-to-line ?v dd ?0.7 ? v output impedance (clkout, multout) r out single-ended 84 100 116 ? output short to gnd (clkout, multout) i sc(?) ?25tbdma output short to v dd (clkout, multout) i sc(+) tbd ?15 ? ma input voltage low (lvttl inputs) v il ?? .8v input voltage high (lvttl inputs) v ih 2.0 ? ? v input low current (lvttl inputs) i il ?25tbd a input high current (lvttl inputs) i ih ?25tbd a output voltage low (lvttl outputs) v ol i o = 2 ma ? ? 0.4 v output voltage high (lvttl outputs) v oh i o = 2 ma 2.0 ? ? v input impedance (lvttl inputs) r in 100 ? ? k ? pwrdn/cal internal pulldown current i pwrdn v pwrdn 0.8 v tbd 25 tbd a *note: the clkin and refclk inputs may be driven differentially or single-endedly. when driving single-endedly, the voltage swing of the signal applied to the active input must exceed the specified minimum differential input voltage swing (v id min) and the unused input must be ac-coupled to ground. when driving differentially, the difference between the positive and negative input signals must exceed v id min. (each individual input signal needs to swing only half of this range.) in either case, the voltage applied to any individual pin (clkin+, clkin?, refclk+, or refclk?) must not exceed the specified maximum input voltage range (v is max).
SI5310 preliminary rev. 0.6 7 table 3. ac characteristics (v dd = 2.5 v 5%, t a = ?40c to 85c) parameter symbol test condition min typ max unit clkin frequency range * 9.375 ? 668 mhz clkin duty cycle tbd ? tbd % refclk range * 9.375 ? 167 mhz refclk duty cycle c duty 40 50 60 % refclk frequency to le ra n c e c tol ?100 ? 100 ppm multout clock rate multout = 0 multout = 1 f mult 600 150 ? ? 668 167 mhz output rise time (clkout, multout) t r figure 4 ? 100 tbd ps output fall time (clkout, multout) t f figure 4 ? 100 tbd ps input rise time (clkin, refclk) t r figure 4 ? ? tbd ps input fall time (clkin, refclk) t f figure 4 ? ? tbd ps clkin to multout delay multsel = 0 multsel = 1 t ci-m figure 3 tbd tbd 150 3.4 tbd tbd ps ns multout to clkout delay multsel = 0 multsel = 1 t m-co figure 3 tbd tbd 1/f mult +160 960 tbd tbd ps ps input return loss 100 khz?2.5 ghz 2.5 ghz?4.0 ghz 18.7 tbd ? ? ? ? db *note: see table 9.
SI5310 8 preliminary rev. 0.6 table 4. ac characteristics (pll performance characteristics) (v dd = 2.5 v 5%, t a = ?40c to 85c) parameter symbol test condition min typ max unit jitter tolerance (multsel = 0, multout = 600 to 668 mhz) j tol(pp) see table 5 jitter tolerance (multsel = 1, multout = 150 to 167 mhz) j tol(pp) see table 6 jitter generation (multout, clkout) (multsel = 0, multout = 600 to 668 mhz)* j gen(rms) clock input (mhz) = 37.500 to 41.750 ?1.9tbdps rms clock input (mhz) = 75.000 to 83.500 ?1.2tbdps rms clock input (mhz) = 150.000 to 167.000 ?0.9tbdps rms clock input (mhz) = 300.000 to 334.000 ?0.5tbdps rms clock input (mhz) = 600.000 to 668.000 ?0.5tbdps rms jitter generation (multout, clkout) (multsel = 1, multout = 150 to 167 mhz)* j gen(rms) clock input (mhz) = 9.375 to 10.438 ?5.8tbdps rms clock input (mhz) = 18.750 to 20.875 ?3.2tbdps rms clock input (mhz) = 37.500 to 41.750 ?2.2tbdps rms clock input (mhz) = 75.000 to 83.500 ?1.4tbdps rms clock input (mhz) = 150.000 to 167.000 ?1.3tbdps rms jitter transfer bandwidth (multsel = 0, multout = 600 to 668 mhz)* j bw clock input (mhz) = 37.500 to 41.750 ?85tbdkhz clock input (mhz) = 75.000 to 83.500 ?170tbdkhz clock input (mhz) = 150.000 to 167.000 ?340tbdkhz clock input (mhz) = 300.000 to 334.000 ?680tbdkhz clock input (mhz) = 600.000 to 668.000 ?1360tbdkhz *note: see pll performance section of this document for test descriptions.
SI5310 preliminary rev. 0.6 9 jitter transfer bandwidth (multsel = 1, multout = 150 to 167 mhz)* j bw clock input (mhz) = 9.375 to 10.438 ?21tbdkhz clock input (mhz) = 18.750 to 20.875 ?43tbdkhz clock input (mhz) = 37.500 to 41.750 ?85tbdkhz clock input (mhz) = 75.000 to 83.500 ?170tbdkhz clock input (mhz) = 150.000 to 167.000 ?340tbdkhz jitter transfer peaking (multsel = 0, multout = 600 to 668 mhz)* j p clock input (mhz) = 37.500 to 41.750 ?0.12tbddb clock input (mhz) = 75.000 to 83.500 ?0.06tbddb clock input (mhz) = 150.000 to 167.000 ?0.03tbddb clock input (mhz) = 300.000 to 334.000 ?0.02tbddb clock input (mhz) = 600.000 to 668.000 ?0.01tbddb jitter transfer peaking (multsel = 1, multout = 150 to 167 mhz)* j p clock input (mhz) = 9.375 to 10.438 ?0.12tbddb clock input (mhz) = 18.750 to 20.875 ?0.06tbddb clock input (mhz) = 37.500 to 41.750 ?0.03tbddb clock input (mhz) = 75.000 to 83.500 ?0.02tbddb clock input (mhz) = 150.000 to 167.000 ?0.01tbddb acquisition time t aq after falling edge of pwrdn/cal 1.45 1.5 1.7 ms from the return of valid clkin 40 60 150 s frequency difference at which pll goes out of lock (refclk compared to the divided down vco clock) lol tbd 600 tbd ppm frequency difference at which pll goes into lock (refclk compared to the divided down vco clock) lock tbd 300 tbd ppm table 4. ac characteristics (pll performance characteristics) (continued) (v dd = 2.5 v 5%, t a = ?40c to 85c) parameter symbol test condition min typ max unit *note: see pll performance section of this document for test descriptions.
SI5310 10 preliminary rev. 0.6 table 5. minimum jitter tolerance in nanoseconds* (multsel = 0, multout = 600 to 668 mhz) frequency (hz) 37.5? 41.75 mhz clock input 75?83.5 mhz clock input 150?167 mhz clock input 300?334 mhz clock input 600?668 mhz clock input <300 25.0 25.0 25.0 25.0 tbd 25k 2.33 4.67 9.33 16.7 tbd 250k 0.67 0.83 1.17 2.17 tbd >1m 0.50 0.58 0.67 0.67 tbd *note: measured using sinusoidal jitter at stated test condition frequency. table 6. minimum jitter tolerance in nanoseconds* (multsel = 1, multout = 150 to 167 mhz) frequency (hz) 9.375? 10.438 mhz clock input 18.75? 20.875 mhz clock input 37.5?41.75 mhz clock input 75?83.5 mhz clock input 150?167 mhz clock input <300 tbd 66.7 66.7 100 tbd 6.5k tbd 18.0 36.7 66.7 tbd 65k tbd 3.33 4.67 8.00 tbd 325k tbd 2.67 2.67 3.33 tbd >1m tbd 2.00 2.33 2.67 tbd *note: measured using sinusoidal jitter at stated test condition frequency. table 7. absolute maximum ratings parameter symbol value unit dc supply voltage v dd ?0.5 to 2.8 v lvttl input voltage v dig ?0.3 to 3.6 v differential input voltages v dif ?0.3 to (v dd + 0.3) v maximum current any output pin 50 ma operating junction temperature t jct ?55 to 150 c storage temperature range t stg ?55 to 150 c lead temperature (soldering 10 seconds) 300 c esd hbm tolerance (100 pf, 1.5 k ? ) clkin+, clkin?, refclk+, refclk?, all other pins ? ? 1 1.5 kv kv note: permanent device damage may occur if the above absolute maximum ratings are exceeded. functional operation should be restricted to the conditions as specified in the operational sections of this data sheet. exposure to absolute maximum rating conditions for extended periods may affect device reliability. table 8. thermal characteristics parameter symbol test condition value unit thermal resistance junction to ambient ? ja still air 38 c/w
SI5310 preliminary rev. 0.6 11 figure 5. SI5310 typical application circuit vdd refclk+ refclk? pwrdn/cal lol clkin+ clkin? gnd multsel clock input system reference clock multout+ multout? clkout+ clkout? 0.1 f regenerated clock multiplied clock lvttl control inputs loss-of-lock indicator SI5310 2200 pf 20 pf rext 10 k ? ? ? ? vdd (1%) (1%) (1%) (1%)
SI5310 12 preliminary rev. 0.6 functional description the SI5310 is an integrated clock multiplier and clock regenerator device based on silicon laboratories dspll? technology. the dspll phase locks to the clock input signal (clkin) and generates a phase- locked output clock (multout) at a multiple of the input clock frequency. the dspll is also employed to regenerate an output clock (clkout) that is a jitter- attenuated version of the input clock with clean rising and falling edges. the multout output is configured to operate in either the 150?167 mhz or the 600?668 mhz frequency range using the multsel control input. a reference clock input signal (refclk) is used by the dspll as a reference for determination of the pll lock status. for convenience, refclk can be provided at any one of five frequencies, each a multiple of the clkin frequency. the refclk rate is automatically detected, so no control inputs are needed for configuration. the refclk input can be synchronous or asynchronous with respect to the clkin input. the operating ranges for the clkin, clkout, multout, and refclk signals are indicated in table 9. typical values for several applications are presented in table 10. table 9. clkin, clkout, multout, refclk operating ranges multsel clkin range (mhz) refclk = 2 n x clkin 100 ppm (see note 2) clkout multout 0 (multout = 600?668 mhz) 37.500?41.750 n = ?2, ?1, 0, 1, or 2 1xclkin 16xclkin 75.000?83.500 n = ?3, ?2, ?1, 0, or 1 1xclkin 8xclkin 150.000?167.000 n = ?4, ?3, ?2, ?1, or 0 1xclkin 4xclkin 300.000?334.000 n = ?5, ?4, ?3, ?2, or ?1 1xclkin 2xclkin 600.000?668.000 n = ?6, ?5, ?4, ?3, or ?2 see note 1 1xclkin 1 (multout = 150?167 mhz) 9.375?10.438 n = 0, 1, 2, 3, or 4 1xclkin 16xclkin 18.750?20.875 n = ?1, 0, 1, 2, or 3 1xclkin 8xclkin 37.500?41.750 n = ?2, ?1, 0, 1, or 2 1xclkin 4xclkin 75.000?83.500 n = ?3, ?2, ?1, 0, or 1 1xclkin 2xclkin 150.000?167.000 n = ?4, ?3, ?2, ?1, or 0 see note 1 1xclkin note: 1. the clkout output is not valid for multout:clkin ratios of 1:1 (multout = 1 x clkin.) 2. the refclk input can be set to any one of the five clkin multiples indicated. the refclk input can be asynchronous to the clkin input, but must be within 100 ppm of the stated clkin multiple.
SI5310 preliminary rev. 0.6 13 table 10. clock values for typical applications clkin (mhz) refclk input (mhz) multsel clkout (mhz) multout output (mhz) sonet/sdh 9.72 9.72 1 9.72 155.52 19.44 19.44 1 19.44 155.52 38.88 38.88 1 38.88 155.52 0 38.88 622.08 77.76 77.76 1 77.76 155.52 0 77.76 622.08 155.52 155.52 1 ? 155.52 0 155.52 622.08 311.04 9.72, 19.44, 38.88, 77.76, or 155.52 0 311.04 622.08 622.08 9.72, 19.44, 38.88, 77.76, or 155.52 0 ? 622.08 gigabit ethernet 9.77 9.77 1 9.77 156.25 19.53 19.53 1 19.53 156.25 39.06 39.06 1 39.06 156.25 0 39.06 625 78.125 78.125 1 78.125 156.25 0 78.125 625 156.25 156.25 1 ? 156.25 0 156.25 625 312.5 9.77, 19.53, 39.06, 78.125, or 156.25 0 312.5 625 625 9.77, 19.53, 39.06, 78.125, or 156.25 0 ? 625.00 sonet/sdh fec (15/14) 10.41 10.41 1 10.41 166.63 20.83 20.83 1 20.83 166.63 41.66 41.66 1 41.66 166.63 0 41.66 666.51 83.31 83.31 1 83.31 166.63 0 83.31 666.51 166.63 166.63 1 ? 166.63 0 166.63 666.51 333.26 10.41, 20.83, 41.66, 83.31, or 166.63 0 333.26 666.51 666.51 10.41, 20.83, 41.66, 83.31, or 166.63 0 ? 666.51
SI5310 14 preliminary rev. 0.6 dspll ? the pll structure (shown in figure 1 on page 4) utilizes silicon laboratories' dspll? technology to produce superior jitter performance while eliminating the need for external loop filter components found in traditional pll implementations. this is achieved by using a digital signal processing (dsp) algorithm to replace the loop filter commonly found in analog pll designs. this algorithm processes the phase detector error term and generates a digital control value to adjust the frequency of the voltage controlled oscillator (vco). the technology produces clocks with less jitter than is generated using traditional methods. in addition, because external loop filter components are not required, sensitive noise entry points are eliminated, thus making the dspll less susceptible to board-level noise sources. clock multiplier the dspll phase locks to the clock input signal (clkin) and generates an output clock (multout) at a multiple of the input clock frequency. the multout output is configured to operate in either the 150? 167 mhz frequency range or in the 600?668 mhz frequency range using the multsel control input as indicated in table 9. values for typical applications are given in table 10. the amount of jitter present in the multout output is a function of the dspll jitter transfer function and jitter generation characteristic. details are provided in the pll performance section of this document. (see figures 6 and 7.) the amount of jitter that the dspll can tolerate on the clkin input is specified in tables 5 and 6. the dspll implementation in the SI5310 is insensitive to the duty cycle of the clkin input. the multout output will continue to exhibit a very good duty cycle characteristic even when the clkin input duty cycle is degraded. 1x multiplication the SI5310 clock multiplier function may also be utilized as a 1x multiplier in order to provide jitter attenuation and duty cycle correction without multiplication of the input clock frequency. note: when the SI5310 is configured as a 1:1 multiplier, the clkout output is not valid. clock regeneration the dspll is used to regenerate a jitter-attenuated version of the clkin input, resulting in a ?clean? clkout output with sharp rising and falling edges. the clkout output is a resampled version of the clkin input with all clkout transitions occurring synchronously with the rising edges of the multout output. the rising edges of clkout are insensitive to the location of the falling edges of the clkin input. thus the period of clkout, measured rising edge to rising edge, is not affected by the clkin duty cycle or by jitter on the falling edge of clkin. the falling edges of clkout may be affected by the location of the clkin falling edges as follows: if the duty cycle error of clkin is significant relative to the period of multout, then 1. the clkout duty cycle may deviate from 50% (the falling edge of clkout will be time quantized to the nearest rising edge of multout.) 2. jitter on the falling edges of clkin may result in a clkout duty cycle that alternates between two discrete values. note: when the SI5310 is configured as a 1:1 multiplier, the clkout output is not valid. reference clock the reference clock input (refclk) is used to center the dspll and also to act as a reference for determination of the pll lock status. refclk is a multiple of the clkin frequency, and can be provided in any one of five frequency ranges (9.375?10.438 mhz, 18.78?20.875 mhz, 37.500?41.750 mhz, 75.00? 83.50 mhz, or 150?167.00 mhz). the refclk rate is automatically detected by the SI5310, so no control inputs are needed for refclk frequency selection. the refclk input may be synchronous or asynchronous with respect to the clkin input. the frequency relationship between refclk and clkin is indicated in table 9. in many applications, it may be desirable to tie refclk and clkin together and drive them from the same clock source. the SI5310 is insensitive to the phase relationship between clkin and refclk, so these differential inputs may be driven in phase or 180 out of phase if this simplifies board layout. values for typical applications are given in table 10. dspll lock detection (loss-of-lock) the SI5310 provides lock-detect circuitry that indicates whether the dspll has frequency locked with the incoming clkin signal. the circuit compares the frequency of a divided down version of the multiplier output with the frequency of the supplied reference clock. if the divided multiplier output frequency deviates from that of the reference clock by the amount specified in table 4 on page 8, the pll is declared out of lock, and the loss-of-lock (lol) pin is asserted. while out of lock, the dspll will try to reacquire lock
SI5310 preliminary rev. 0.6 15 with the input clock. during reacquisition, the multiplier output (multout) will drift over a range of approximately 1% relative to the supplied reference clock. the lol output will remain asserted until the divided multiplier output frequency differs from the refclk frequency by less than the amount specified in ta b l e 4 . note: lol is not asserted during pwrdn/cal. pll performance the SI5310 dspll circuitry is designed to provide low jitter generation, high jitter tolerance, and a well- controlled jitter transfer function with low peaking. each of these key performance parameters is described more fully in the following sections. jitter tolerance jitter tolerance for the SI5310 is defined as the maximum peak-to-peak sinusoidal jitter that can be added to the incoming clock before the pll exceeds its allowable operating range and loses lock. the tolerance is a function of the jitter frequency, the incoming clock rate, and the multsel setting. the jitter tolerance for specified jitter frequencies and input clock rates is given in tables 5 and 6. jitter transfer jitter transfer is defined as the ratio of output signal jitter to input signal jitter for a specified jitter frequency. the jitter transfer characteristic determines the amount of input clock jitter that will be passed on to the SI5310 clkout and multout outputs. the dspll technology used in the SI5310 provides a tightly controlled jitter transfer curve because many of the pll gain parameters are determined by digital signal processing algorithms which do not vary over supply voltage, process, and temperature. in a system application, a well-controlled transfer curve minimizes the output clock jitter variation from board to board, providing more consistent system level jitter performance. the jitter transfer characteristic is a function of the multsel setting and the input clock rate. higher input clock rates produce higher bandwidth transfer functions with lower jitter peaking. table 4 gives the 3 db bandwidth and peaking values for specified input clock rates and multsel settings. figures 6 and 7 show a family of jitter transfer curves for different input clock rates. jitter generation jitter generation is defined as the amount of jitter produced at the output of the device with a jitter free input clock. generated jitter arises from sources within the vco and other pll components. jitter generation is a function of multsel setting and input clock frequency. for clock multiplier applications, the higher the multiplier ratio desired, the larger the jitter generation. table 4 gives the jitter generation values for specified multsel settings and input clock rates. device power-down the SI5310 pwrdn/cal input can be used to hold the device in a power-down state when not in use. when the pwrdn/cal input is asserted (set high), the clkout and multout output drivers are disabled and the positive and negative terminals of the clkout and multout outputs are each tied to vdd through 100 ? on-chip resistors. this feature is useful in reducing power consumption in applications that employ redundant clock sources. when pwrdn/cal is released (set to low) the digital logic is reset to a known initial condition and the dspll circuitry is recalibrated and will begin to lock to the incoming clock. pll self-calibration SI5310 device provides an internal self-calibration function that optimizes the loop gain parameters within the internal dspll. self-calibration is initiated by a high-to-low transition of the pwrdn/cal signal while a valid reference clock is supplied to the refclk input. for optimal jitter performance, the supply voltage should be stable at 2.5 v 10% when calibration is initiated. the pwrdn/cal signal should be held high for at least 1 s after the supply has stabilized before transitioning low to initiate self-calibration. see silicon laboratories application note an42 for suggested methods of generating the pwrdn/cal signal for initiation of self-calibration. device grounding the SI5310 uses the gnd pad on the bottom of the 20- pin micro leaded package (mlp) for device ground. this pad should be connected directly to the analog supply ground. see figures 10 and 11 for the ground (gnd) pad location. bias generation circuitry the SI5310 makes use of an external resistor to set internal bias currents. the external resistor allows precise generation of bias currents which significantly reduces power consumption compared with traditional implementations that use an internal resistor. the bias generation circuitry requires a 10 k ? (1%) resistor connected between rext and gnd.
SI5310 16 preliminary rev. 0.6 figure 6. pll jitter transfer functions, multsel = 0 (multout = 600?668 mhz) differential input circuitry the SI5310 provides differential inputs for both the input clock (clkin) and the reference clock (refclk) inputs. an example termination for these inputs is shown in figure 8. in applications where direct dc coupling is possible, the 0.1 f capacitors may be omitted. the clkin and refclk input amplifiers require input signals with minimum differential peak-to- peak voltages as specified in table 2 on page 6. figure 7. pll jitter transfer functions, multsel = 1 (multout = 150?167 mhz) differential output circuitry the SI5310 utilizes a current mode logic (cml) architecture to output both the regenerated clock (clkout) and the multiplied clock (multout). an example of output termination with ac coupling is shown in figure 9. for applications in which direct dc coupling is possible, the 0.1 f capacitors may be omitted. the differential peak-to-peak voltage swing of the cml is listed in table 2 on page 6. 10 3 10 4 10 5 10 6 ?9 ?8 ?7 ?6 ?5 ?4 ?3 ?2 ?1 0 clkin=39mhz clkin=622mhz 10 3 10 4 10 5 10 6 ? 9 ? 8 ? 7 ? 6 ? 5 ? 4 ? 3 ? 2 ? 1 0 clkin=9.7mhz clkin=155mhz
SI5310 preliminary rev. 0.6 17 figure 8. input termination for clkin and refclk (ac coupled) figure 9. output termination for clkout and multout (ac coupled) clock source SI5310 0.1 f 0.1 f zo = 50 ? zo = 50 ? clkin +, rfclk + clkin ?, rfclk ? 2.5 k ? 2.5 k ? 10 k ? 10 k ? 102 ? vdd gnd clkout?, multout? 50 ? 50 ? 0.1 f 0.1 f zo = 50 ? zo = 50 ? SI5310 vdd vdd 100 ? 100 ? vdd vdd clkout+, multout+
SI5310 18 preliminary rev. 0.6 pin descriptions: SI5310-bm figure 10. SI5310-bm pin configuration table 11. SI5310 pin descriptions pin # pin name i/o signal level description 1rext external bias resistor. this resistor is used by onboard circuitry to estab- lish bias currents within the device. this pin must be connected to gnd through a 10 k ? ( 1 %) resis- tor. 2, 7, 11, 14 vdd 2.5 v supply voltage. nominally 2.5 v. 3, 8, 18, and gnd pad gnd gnd supply ground. nominally 0.0 v. the gnd pad found on the bottom of the 20-pin micro leaded package (see figure 11) must be connected directly to supply ground. 4, 5 refclk+, refclk? i see table 2 differential reference clock. the reference clock sets the initial operating fre- quency used by the onboard pll for clock regener- ation and multiplication. additionally, the reference clock is used as a reference in generation of the lol output and to bound the frequency drift of multout when clkin is not present. 6lololvttl loss of lock. this output is driven high when a divided version of the clock multiplier output deviates from the refer- ence clock frequency by the amount specified in table 4 on page 8. 9, 10 clkin+, clkin? i see table 2 differential clock input. differential input clock from which multout is derived. 1 2 3 4 5 6 7 8 9 13 14 15 16 rext vdd gnd refclk+ refclk? pwrdn vdd clkout+ clkout? vdd 12 11 10 gnd 17 18 19 20 nc multsel gnd multout+ multout? lol vdd gnd clkin+ clkin? pad top view
SI5310 preliminary rev. 0.6 19 12, 13 clkout?, clkout+ ocml differential clock output. the clock output signal is a regenerated version of the input clock signal present on clkin. it is phase aligned with multout and is updated on the rising edge of multout. note: connection of an improperly terminated transmission line to the clkout output can cause reflections that may adversely affect the performance of the multout output. if the clkout output is not used, these pins should be either tied to v dd (recommended), left unconnected, or connected to a properly terminated transmission line. 15 pwrdn/cal i lvttl power down. to shut down the high-speed outputs and reduce power consumption, hold this pin high. for normal operation, hold this pin low. calibration. to initiate an internal self-calibration, force a high- to-low transition on this pin. (see "pll self-calibra- tion?" on page 15.) note: this input has a weak internal pulldown. 16, 17 multout?, multout+ ocml differential multiplier output. the multiplier output is generated from the signal present on clkin. in the absence of clkin, the refclk is used to bound the frequency of mul- tout according to table 4 on page 8. note: connection of an improperly terminated transmission line to the multout output can cause reflections that may adversely affect the clkout output. if the multout output is not used, these pins should be either tied to v dd (recommended), left unconnected, or connected to a properly terminated transmission line. 19 multsel i lvttl multiplier rate select. this pin configures the onboard pll-based clock multiplier for clock generation at one of two user selectable clock rates. note: this input has a weak internal pulldown. 20 nc no connect. this pin should be tied to ground. table 11. SI5310 pin descriptions (continued) pin # pin name i/o signal level description
SI5310 20 preliminary rev. 0.6 ordering guide table 12. ordering guide part number package temperature SI5310-bm 20-pin mlp ?40c to 85c
SI5310 preliminary rev. 0.6 21 bm package outline figure 11 illustrates the package details for the SI5310-bm. table 13 lists the values for the dimensions shown in the illustration. figure 11. 20-pin micro leaded package (mlp) table 13. package diagram dimensions symbol millimeters symbol millimeters min nom max min nom max a ? 0.85 1.00 e1 3.75 bsc a1 0.00 0.01 0.05 e2 1.95 2.10 2.25 a2 ? 0.65 0.80 n 20 a3 0.20 ref nd 5 b 0.18 ? 0.30 ne 5 d 4.00 bsc l 0.50 0.60 0.75 d1 3.75 bsc p 0.24 0.42 0.60 d2 1.95 2.10 2.25 q 0.30 0.40 0.65 e 0.50 bsc r 0.13 0.17 0.23 e 4.00 bsc ??12 top view 0.50 dia. d1/2 d1 d/2 d e1/2 e/2 e1 e a 2x 0.20 b c 0.10 b a m c a n bottom view seating plane n 56 3 2 2 3 b e 1 1 0.05 c l e l c for odd terminal/side for even terminal/side c c c 2x c 0.25 0.25 2x b 0 l ref. (nd-1)xe (ne-1)xe ref. 4 a1 8. 4x p 4x q r a c 10 c 4x p b 2x a c 0.20 a2 a3 d2 d2/2 e2 e2/2 terminal tip e 4 section "c-c" scale: none b a1 11 package by using indentation mark or other feature of package body. the pin #1 identifier must be existed on the top surface of the die thickness allow able is 0.305mm maximum(.012 i nches maximum) notes: dimensioning & tolerances conform to asme y14.5m. - 1994. n is the number of terminals. nd is the number of terminals in x-direction & ne is the number of terminals in y-direction. dimension b applies to plated terminal and is measured betw een 0.20 and 0.25mm from terminal tip. exact shape and size of this feature is optional. 7. all dimensions are in millimeters. the shape show n on four corners are not actual i/o. package w arpage max 0.05mm. 9. applied for exposed pad and terminals. exclude embedding part of exposed pad from measuring. applied only for terminals. 3. 4. 5. 6. 8. 10. 11. 1. 2.
SI5310 22 preliminary rev. 0.6 contact information silicon laboratories inc. 4635 boston lane austin, tx 78735 tel: 1+(512) 416-8500 fax: 1+(512) 416-9669 toll free: 1+(877) 444-3032 email: productinfo@silabs.com internet: www.silabs.com silicon laboratories, silicon labs, and dspll are trademarks of silicon laboratories inc. other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders. the information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. silicon laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resu lting from the use of information included herein. additionally, silicon laboratories assumes no responsibility for the functioning of und escribed features or parameters. silicon laboratories reserves the right to make changes without further notice. silicon laboratories makes no wa rranty, rep- resentation or guarantee regarding the suitability of its products for any particular purpose, nor does silicon laboratories as sume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation conse- quential or incidental damages. silicon laboratories products are not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other application in which the failure of the silicon laboratories product could create a s ituation where per- sonal injury or death may occur. should buyer purchase or use silicon laboratories products for any such unintended or unauthor ized ap- plication, buyer shall indemnify and hold silicon laboratories harmless against all claims and damages.

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